1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a manufacturing method of a semiconductor device including an electrode formed in a recessed structure and the semiconductor device.
2. Description of the Related Art
There is known an HEMT (High Electron Mobility Transistor) as a high speed transistor. The HEMT is a transistor capable of operating at high-speed by a configuration where a two-dimensional electron gas is formed in a laminated semiconductor structure by utilizing a compound semiconductor heterojunction so as to increase the mobility of electron. In the HEMT, the two-dimensional electron gas does not flow on the outermost surface in the laminated semiconductor structure but flows near the interface of the laminated semiconductor structure, so that a contact with a drain and a source needs to be formed in the laminated semiconductor structure so as to be connected directly to the interface.
FIG. 5 is a cross-sectional view illustrating a representative configuration of the contact structure in the source or drain region in the HEMT. The HEMT illustrated in FIG. 5 uses a wide band gap GaN to meet high power requirements. A buffer layer 202 is formed on a substrate 201 made of monocrystalline silicon or the like by epitaxial growth, and a GaN layer 203 serving as a channel layer is formed by epitaxial growth on the buffer layer 202. On the GaN layer 203, an AlGaN layer 204 serving as a carrier supply layer is formed by epitaxial growth. At this time, an abrupt junction is formed at the interface between the GaN layer and AlGaN layer so as to allow formation of the two-dimensional electron gas. The two-dimensional electron gas is formed very thin on the GaN side of the interface, and the electrons in this layer exhibit considerably high mobility. Note that there is also a case where a cap GaN layer is formed on the AlGaN layer 204.
The two-dimensional electron gas is formed only near the interface between the GaN layer 203 and AlGaN layer 204. Therefore, in order to make a contact (electrical contact) with the two-dimensional electron gas, etching is performed deeply enough to a portion below the interface to form a recessed portion (recessed region) for subsequent formation of an electrode 205 in the recessed portion. FIGS. 6A to 6G are process cross-sectional views illustrating an example of a manufacturing process of this structure. The illustrations of the substrate 201 and buffer layer 202 are omitted here.
As illustrated in FIG. 6A, a photoresist pattern 206 having an opening at a portion at which the recessed region is formed by photolithography on the laminated semiconductor structure of the GaN layer 203 and AlGaN layer 204. Then, as illustrated in FIG. 6B, the AlGaN layer 204 and GaN layer 203 are removed by dry etching using the photoresist pattern 206 as a mask, and the photoresist pattern 206 is removed, whereby a recessed region 207 as illustrated in FIG. 6C is formed. As a result, the GaN/AlGaN interface is exposed from the side surface of the recessed region 207. Then, after an electrode material 208 is formed over the entire resultant exposed surface as illustrated in FIG. 6D, a photoresist pattern 209 is formed by lithography as illustrated in FIG. 6E. Then, as illustrated in FIG. 6F, dry etching is applied to the electrode material 208 using the photoresist pattern 209 as a mask. After removal of the photoresist pattern 209, an electrode 205 having a predetermined pattern is obtained as illustrated in FIG. 6G. Note that the gate of the HEMT is formed outside the region illustrated in FIGS. 5 and 6.
In order to reduce the on-state resistance of the HEMT, a contact resistance in the source or drain needs to be reduced. Thus, a reduction in a variation of the contact resistance or resistance value between the two-dimensional electron gas and electrode 205 is required. However, in this structure, the contact area between the electrode and layer (two-dimensional electron gas layer) through which current flows is considerably smaller than in a general MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using an electrical contact with the surface of the source or drain. Therefore, it is not easy to reduce a variation of the contact resistance or resistance value.
In order to cope with the above situation, Japanese Patent Application No. JP-A-2007-165446 (Patent Document 1) discloses a technique in which many concavities and convexities are formed on the side surface (surface at which the electrode 205 and GaN/AlGaN layers 203, 204 contact each other) of the recessed region in FIG. 5. This structure allowed the contact area between the electrode and two-dimensional electron gas layer to be substantially increased, thereby reducing a variation of the contact resistance or resistance value in the source or drain.
However, in order to achieve the above structure including the technique disclosed in Patent Document 1, two photolithography processes are required in total for formation of the recessed region 207 and electrode 205 as illustrated in FIGS. 6A to 6G. Especially, in the lithography (FIG. 6E) for formation of the electrode 205, it is necessary to achieve alignment with the recessed region 207 that has already been formed with sufficient accuracy. When the positions of the electrode 205 and recessed region 207 are displaced from each other due to poor accuracy of the alignment, contact between the electrode 205 and two-dimensional electron gas layer becomes incomplete in some cases, which may accordingly increase the resistance of this portion to degrade the reliability of the device.
As a result, it is necessary to make the width of the electrode 205 larger than that of the recessed region 207 in accordance with the alignment accuracy by an amount corresponding to, e.g., the width of regions (overlapping regions) indicated by two-headed arrows of FIG. 6G. For example, the overlapping regions each have a width of 2 μm. In this case, it is necessary to set the interval (interval between the side surface of the recessed region 207 in the source and side surface of the recessed region 207 in the drain) between the source and drain to a larger value, with the result that the on-state resistance is increased.
The same can be said for the structure disclosed in Patent Document 1. Further, in the case of the structure of Patent Document 1, current concentrates on the portion at which the interval between the concavities and convexities on the edge surface of the recessed region in the source and concavities and convexities on the edge surface of the recessed region in the drain becomes small, causing a reduction in reliability on prolonged use.
Thus, in a semiconductor device having an electrode formed in the recessed structure, it has been difficult to reduce the on-state resistance and increase reliability of the device.